In certain applications, power-on-read (POR) time can be an important specification emphasized by customers. In one exemplary embodiment, when power is supplied to a memory device, the memory device goes through a series of initialization stages. During this POR time, power-on-read algorithms are performed. The POR algorithms can execute steps necessary to put the memory device (i.e., the flash memory's microcontroller, SRAM, and registers) into a state ready to receive commands, such as read/write and erase requests.
One component of the power-on-read time is the time required for loading redundancy information. Such information (which can take more than 10 percent of the total POR time) is used to keep track of redundant sectors. An exemplary memory device can be divided into sectors, with the total number of available sectors divided into normal operation sectors and redundant sectors. When a normal operation sector has been identified and flagged as bad, one of the redundant sectors can be used in the place of the bad sector. In one exemplary embodiment, a redundancy register can replace the address of the bad sector with the address of one of the redundant sectors. As discussed in detail below, a flash memory device can contain a plurality of normal sectors, a plurality of redundant sectors and a look-up table storing the redundancy information that will contain information about the current usage of the redundant sectors (whether a particular redundant sector is currently being used to replace a bad normal sector).
Designing POR times to meet customer requirements has been getting more challenging, especially as flash memory devices are becoming more advanced and larger in terms of memory densities. For example, while an exemplary 256 Mb memory device has 8 redundant sectors, an exemplary 16 Gb memory device has 64 redundant sectors. Currently, there are two alternatives for speeding up POR times: pure hardware implementation and improved software efficiencies. There are at least three disadvantages to a pure hardware implementation. First, there is no flexibility. Once a particular hardware embodiment has been realized physically, there is no easy way to make modifications to it. Second, such modifications to the hardware will usually result in an increased die size. Creating new hardware embodiments that result in increased die size can also result in increased production costs. Third, pure hardware implementation can be more complicated than software implementations.
Therefore, software implementations are a preferred choice for power-on-read implementations when tight POR time requirements exist. However, software implementation has corresponding challenges and disadvantages of its own. For example, more than 10 percent of the actual power-on-read time can be spent in loading the redundancy information. In addition to the extended loading time concerns for redundancy information, larger memory devices require the loading and storage of ever larger quantities of redundancy information. With the available storage space also at a premium, especially in BiST loading schemes with additional memory requirements; software solutions for efficient redundancy information loading are sometimes not possible for larger memory devices. Such loading of redundancy information is inefficient and as discussed above, worsens with larger memory capacities. Therefore, it is desirable to improve the redundancy information loading to reduce the POR time.